Pulse width modulation (PWM) controllers are effectively being used to control voltage levels in power supplies and to control rotational speed and direction of motors. For motor control, a direct current (DC) power source is switched on and off at various rates to produce an alternating current (AC) waveform that is used to control the speed and rotational direction of the motor. Referring to FIG. 1, depicted is a schematic block diagram of a pulse width modulation (PWM) power controller 102 and a schematic connection diagram of a power driver circuit 106. Typically a “half-bridge” power transistor configuration (power transistors 110 and 112), e.g., power MOSFET, SCR, triac, etc., are controlled by two complementary PWM signals, PWMH 220 and PWML 222, only one of which is on at any time. To insure that there can be no “on” overlap of the two complementary PWM signals, “dead time” is introduced between these two complementary PWM signals, PWMH 220 and PWML 222 (generally refer to FIG. 2). The “dead time” function insures that no current spikes are generated when one transistor is turned off while the other transistor is turned on (e.g., no “on” overlap that would cause a short circuit between +V and −V). While dead-time circuits are a required function, they create their own “issues.” The biggest problem with dead-time circuits is that the resultant transistor waveforms are distorted by the inductance of the motor windings. This waveform distortion causes the controlled motor to run roughly at slow motor speeds. A dead-time compensation circuit may be used to correct for the distortion caused by the motor induction.
Referring to FIG. 3, depicted are schematic block diagrams of specific example prior technology embodiments of digital PWM generation systems for generating complementary PWM waveforms having dead time compensation. These prior technologies for dead-time compensation select between two different PWM duty cycles depending on the direction of current flow in the motor load. As shown in FIG. 3(a), a simple dead time compensation circuit uses a multiplexer 306 to select one of two duty cycle values from different duty cycle control registers 302 and 304, depending on the state of a device input 340 (determined by direction of motor current flow). This prior technology embodiment requires a large amount of software “overhead” to constantly compute and load new duty cycle values into the device's duty cycle control registers 302 and 304. As shown in FIG. 3(b), another technology uses a “brute force” method that requires a hardware adder/subtractor 310 that automatically computes the desired compensated dead time values based upon the direction of current flow through the controlled motor and adds/subtracts from the duty values stored in the duty cycle control registers 302 and 304. The hardware implementation of FIG. 3(b) is expensive and complex to implement.